Dynamic random access memory (DRAM) is a major semiconductor product and is utilized in computer core memory and many other consumer devices. Two commonly used layout designs for DRAM memory cells are planar and stacked. In a planar memory cell structure, the cell is built up from the substrate. The cell's capacitor is formed by a dielectric silicon dioxide layer that is laid down between the polysilicon cell plate and the substrate. In a stacked memory cell structure, the cell is built up from the substrate as in the planar memory cell structure. The dielectric layer is partially sandwiched between two layers of polysilicon, yielding a large capacitive surface.
FIG. 1 illustrates a prior art planar capacitor DRAM structure 100 having a 1-bit memory cell. The memory structure 100 includes a MOS transistor 101 and a capacitor 103. The memory structure 100 includes a p-type substrate 102 having n+ dopant diffused areas 105. A tunnel oxide layer 104 is formed over p-type substrate 102 above the n+ dopant areas that function as a source 105a and a drain 105b for MOS transistor 101. A polysilicon layer 106 is formed over the tunnel oxide layer 104. A first portion of the polysilicon layer 106a functions as a control gate for MOS transistor 101. A second portion of the polysilicon layer 106b forms part of the storage capacitor 103. The memory structure 100 may be arranged in one or more arrays. In such an arrangement, each capacitor 103 functions as a memory storage element capable of storing one memory bit. Each MOS transistor 101 controls writing, erasing, and reading of the memory storage element through connections to word lines, bit lines, and sense amplifiers (not shown) as is well known. Because of increased density requirements in consumer electronics, there is a need for memory devices to occupy less space on memory chips. However, there is a lower bound on the size of the storage capacitor in light of issues of data detection and retention, so that increasing density using conventional DRAM designs is very difficult.
FIG. 2 illustrates a prior art stacked capacitorless silicon on insulator (SOI) trapping DRAM (TDRAM) memory structure 200 having a 1-bit memory cell. The memory structure 200 includes a p-type substrate 202. An oxide layer 204, such as SiO2 is formed over the p-type substrate 202, and a silicon layer 206 is formed over the oxide layer 204 to complete the SOI (or silicon-insulator-silicon) layered structure. The silicon layer 206 includes n+ dopant diffused areas 205 that function as a source 205a and a drain 205b. An oxide layer 208 is formed over the silicon layer 206, and a gate oxide layer 210 is formed above the oxide layer 208. The gate oxide layer 210 functions as a control gate. In operation, control voltages are applied to the control gate, source, and drain to inject into or remove charge carriers from the silicon layer 206. Charge is “trapped” in the silicon layer 206, rather than being stored in a storage capacitor. The silicon layer 206 (or “floating body”) functions as a charge storage layer. The SOI layered structure of memory structure 200 may be formed, for example, using an oxygen ion beam implantation process to create a buried SiO2 layer. Alternatively, a wafer bonding process or any one of a number of other methods known in the art may be used. The capacitorless SOI structure 200 requires less space than the conventional planar capacitor DRAM structure 100 of FIG. 1, but there is a need for a memory structure having a simpler fabrication process. Also, because of increased density requirements in consumer electronics, there is a need for memory devices to store more than 1-bit of data per memory cell.
FIG. 3 illustrates a prior art metal-oxide-nitride-nitride-silicon (MONNS) memory structure 300 for a floating-gate EEPROM flash memory having a 1-bit memory cell. The memory structure 300 includes a p-type substrate 302 having n+ dopant diffused areas 303 which function as a source 303a and a drain 303b. A first nitride layer 304, such as silicon nitride (SiN), is formed over the p-type substrate 302. A second nitride layer 306, such as silicon nitride (SiN), is formed over the first nitride layer 304. An oxide layer 308 is formed over the second nitride layer 306. A metal layer 310 is formed over the oxide layer 308. In operation, the second nitride layer 306 acts as the charge trapping and storage layer, while the first nitride layer 304 simply acts as a low barrier height (LBH) dielectric layer. The MONNS flash memory structure 300 has a simpler fabrication process than the capacitorless SOI TDRAM structure 200 of FIG. 2. However, it is not suited for high-speed memory applications such as DRAM. Also, because of increased density requirements in consumer electronics, there is a need for memory devices to store more than 1-bit of data per memory cell.